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august 2015 docid028257 rev 1 1 / 11 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. www.st.com STL7N6F7 n - channel 60 v, 0.021 typ., 7 a stripfet? f7 power mosfet in a powerflat? 2x2 package datasheet - preliminary data figure 1 : internal schematic diagram features order code v ds r ds(on) max i d STL7N6F7 60 v 0.025 7 a ? among the lowest r ds(on) on the market ? excellent figure of merit (fom) ? low c rss /c iss ratio for emi immunity ? high avalanche ruggedness applications ? switching applications description this n-channel power mosfet utilizes stripfet? f7 technology with an enhanced trench gate structure that results in very low on- state resistance, while also reducing internal ca pacitance and gate charge for faster and more efficient switching. table 1: device summary order code marking package packing STL7N6F7 st7n powerflat? 2x2 tape and reel 1 2 3 6 5 4 1 2 3 powerfla t? 2x2 1(d) 2(d) 3(g) 6(d) 5(d) 4(s) d s am 11269v1 bottom view
contents STL7N6F7 2 / 11 d ocid028257 rev 1 contents 1 electrical ratings ............................................................................... 3 2 electrical characteristics ................................................................ . 4 3 test circuits ...................................................................................... 6 4 package information ........................................................................ 7 4.1 powerflat 2x2 package information ............................................... 8 5 revision history .............................................................................. 10
STL7N6F7 electrical ratings docid028257 rev 1 3 / 11 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v ds drain - source voltage 60 v v gs gate - source voltage 20 v i d drain current (continuous) at t pcb = 25 c 7 a i d drain current (continuous) at t pcb = 100 c 4.5 a i dm (1) drain current (pulsed) 28 a p tot total dissipation at t pcb = 25 c 2.4 w t j operating junction temperature - 55 to 150 c t stg storage temperature notes: (1) pulse width limited by safe operating area. table 3: thermal data symbol parameter value unit r thj - pcb (1) thermal resistance junction - pcb max. 52 c/w notes: (1) when mounted on fr - 4 board of 1 inch2, 2oz cu, t < 10 sec.
electrical characteristics STL7N6F7 4 / 11 docid028257 rev 1 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4: on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage i d = 1 ma, v gs = 0 v 60 v i dss zero gate voltage drain current v gs = 0 v , v ds = 60 v 1 a i gss gate - body leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 4 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 3.5a 0.021 0.025 table 5: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 25 v, f = 1 mhz, v gs = 0 v - 450 - pf c oss output capacitance - 210 - pf c rss reverse transfer capacitance - 22 - pf q g total gate charge v dd = 48 v, i d = 7 a v gs = 10 v (see figure 3: "test circuit for gate charge behavior" ) - 8 - nc q gs gate - source charge - tbd - nc q gd gate - drain charge - tbd - nc table 6: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 30 v, i d = 3.5a, r g = 4.7 , v gs = 10 v (see figure 2: "test circuit for resistive load switching times" ) - tbd - ns t r rise time - tbd - ns t d(off) turn - off delay time - tbd - ns t f fall time - tbd - ns
STL7N6F7 electrical characteristics docid028257 rev 1 5 / 11 table 7: source-drain diode symbol parameter test conditions min. typ. max. unit v sd (1) forward on voltage i sd = 7 a, v gs = 0 v - 1.2 v t rr reverse recovery time i d = 7 a, di/dt = 100 a/s v dd = 48 v (see figure 4: "test circuit for inductive load switching and diode recovery times" ) - tbd ns q rr reverse recovery charge - tbd nc i rrm reverse recovery current - tbd a notes: (1) pulsed: pulse duration = 300 s, duty cycle 1.5%
test circuits STL7N6F7 6 / 11 docid028257 rev 1 3 test circuits figure 2 : test circuit for resistive load switching times figure 3 : test circuit for gate charge behavior figure 4 : test circuit for inductive load switching and diode recovery times figure 5 : unclamped inductive load test circuit figure 6 : unclamped inductive waveform figure 7 : switching time waveform
STL7N6F7 package information docid028257 rev 1 7 / 11 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package information STL7N6F7 8 / 11 docid028257 rev 1 4.1 powerflat 2x2 package information figure 8 : powerflat? 2x2 package outline 8368575_rev_c
STL7N6F7 package information docid028257 rev 1 9 / 11 table 8: powerflat? 2x2 mechanical data dim. mm min. typ. max. a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 b 0.25 0.30 0.35 d 1.90 2.00 2.10 e 1.90 2.00 2.10 d2 0.90 1.00 1.10 e2 0.80 0.90 1.00 e 0.55 0.65 0.75 k 0.15 0.25 0.35 k1 0.20 0.30 0.40 k2 0.25 0.35 0.45 l 0.20 0.25 0.30 l1 0.65 0.75 0.85 figure 9 : powerflat? 2x2 recommended footprint (dimensions are in mm) footprint
revision history STL7N6F7 10 / 11 docid028257 rev 1 5 revision history table 9: document revision history date revision changes 27 - aug - 2015 1 first release.
STL7N6F7 docid028257 rev 1 11 / 11 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers s hould obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, select ion, and use of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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